The raster scan display is commonly utilized both in computer systems and in commercial televisions. An image displayed on the screen comprises an array of pixels arranged in rows and columns. The screen is usually refreshed sequentially scan line by scan line from top to bottom. Presently, the refresh rate is usually not lower than 30 Hz. A frame buffer stores the screen refresh pixel data. When any pixel datum in the frame buffer is updated, the screen is refreshed, and the corresponding pixel on the screen is changed.
FIG. 1 schematically illustrates a conventional raster display system. The display system 10 is utilized to display an image on the CRT screen 12. Pixel data which is displayed on the screen 12 is stored in a frame buffer 14. In the conventional display system 10 of FIG. 1, the frame buffer 14 is a dynamic RAM (DRAM).
When the host computer 16 is ready to refresh the DRAM 14, an address is sent to the DRAM 14 from the host computer 16 via the address bus 15 and the multiplexer (MUX) 18. Data to be entered in the DRAM is sent from the host computer 16 to the random access port 20 of the DRAM 14 via the bus 30. Additionally, host access control signals are sent via line 8 to a memory controller circuit 7 which transmits various control signals, such as CAS, RAS, etc., via line 9 to the DRAM 14.
To perform a screen refresh operation, an address is sent from the graphic controller 22 to the DRAM 14 via the bus 17 and the multiplexer 18. The pixel data to be transmitted to the screen 12 in the screen refresh operation is read out of the DRAM 14 at the random access port 20 and is transmitted via the bus 30 to the shift register 24 which serves as a parallel-to-serial converter. The data is converted from digital to analog form using the Digital-to-Analog converter (DAC) 26 and then transmitted to the screen 12. The timing of the shift register 24 is controlled by a video timing signal generated by the graphic controller 22 and transmitted to the shift register 24 via the line 19. The graphic controller 22 is connected to the host computer 16 via the bus 11 and also generates the vertical synchronization signal (VSYNC), the horizontal synchronization signal (HSYNC) and the horizontal and vertial blanking signals which are transmitted via lines 21 to the screen 12 and the DAC 26.
The display system 10 of FIG. 1 has a significant disadvantage. The major problem is that the bus 30 leading to and from the random access port 20 is utilized to receive data from the host computer 16 for frame buffer refresh and to transmit data to the screen 12 for screen refresh. As is known, an increase in screen resolution will increase the time required to refresh the screen. When the required time to refresh the screen reaches a certain level, the host computer 16 will not be able to gain control over the bus 30 and random access port 20 to perform frame buffer refresh operations. This conflict over use of the random access port 20 and bus 30 results in a decrease in the efficiency of operation of the display system.
One way to avoid this kind of conflict is to implement the frame buffer as a video RAM (VRAM) instead of a simple DRAM. A 256K*4 VRAM 40 is illustrated in FIG. 2. The VRAM 40 of FIG. 2 comprises a DRAM array 42 having 512 columns and 512 rows. The VRAM 40 has both a random access port 44 and a serial port 45. The serial port 45 is illustratively formed by a serial access memory (SAM) 46 implemented with a shift register. An entire row of data from the DRAM 42 is transferred to the SAM 46 via lines 47A, 47B and transfer pass gate 43 by an operation which is called a read data transfer (RDT). When a read data transfer operation is carried out, a row of data of the DRAM 42 is transferred to the SAM 46. Thereafter, the data of the SAM 46 may be serially shifted out of the I/O port 49. This is achieved by means of a serial counter 48 which receives a serial clock (SC) as an input. The serial counter increments with each clock of the serial clock thereby outputting a different pixel datum from the SAM 46. Alternatively, the serial counter 48 includes a pointer which points to a starting location in the SAM 46. In this mode of operation, data is serially shifted out of the SAM 46 starting at the location pointed to by this pointer. Illustratively, a TMS44C250 VRAM manufactured by Texas Instruments operates in a fashion similar to the VRAM 40 of FIG. 2.
FIG. 3 illustrates a video display system 10'. The system 10' of FIG. 3 is similar to the system 10 of FIG. 1. The differences are that the frame buffer is now implemented by the VRAM 40 instead of the DRAM 14 as in FIG. 1. In addition, the parallel-to-serial converter 24 is eliminated. In the system 10' of FIG. 3, a frame buffer refresh operation transfers data from the host computer 16 to the random access port 44 of the VRAM 40 via the bus 47. On the other hand, to carry out a screen refresh operation, data is transferred from the serial port 45 in bits-serial format (e.g., 4-bit wide serial format) to the DAC 26 for conversion to analog form for refreshing the display on the screen 12. In the display system 10', the serial clock for use by the serial port 45 of the VRAM 40 is supplied by the graphic controller 22 via the line 48.
In short, in the system 10' of FIG. 3, frame buffer refresh operations and screen refresh operations take place via different ports and utilize different buses, so that the two processes are isolated from each other. Therefore, conflict between the two types of operations over access to the random port 20 and bus 30 of FIG. 1 are substantially resolved.
The problem with the system 10' of FIG. 3 is that the VRAM 40 utilized therein makes very inefficient use of memory capacity. This is illustrated through use of the following example. Consider the case where the screen 12 has a resolution of 900 scan lines with 1152 pixels per scan line. The pixels in each scan line of the display screen are labeled 0,1, . . . , 1151. The scan lines are labeled 1, . . . , 900. The memory arrays of a 256*4 VRAM for storing one 900*1152 frame of pixels for a screen with this format are illustrated in FIG. 4.
The memory capacity of FIG. 4 is divided into two banks, labeled BANK 1 and BANK 2. Each bank comprises four memory arrays. The memory arrays of BANK 1 are labeled VRAM0, VRAM1, VRAM2, VRAM3. Similarly, the memory arrays of BANK 2 are labeled VRAM0,VRAM1,VRAM2,VRAM3. Each memory array is 2.sup.9 .times.2.sup.9 which means that it has 512 rows and 512 column locations per row. Every column location of each row may store the datum of one pixel. The 512 rows of each memory array are labeled 0,1, . . . , 511 in FIG. 4. In this memory arrangement, each row of the VRAMs, VRAM0, VRAM1, VRAM2, VRAM3 is used to store one scan line of the display. The 512 columns of each memory array are labeled 0,1, . . . , 511 in FIG. 4.
The pixels 0, . . . , 1151 of scan line 1 of one frame for the screen 12 are stored in the memory arrays of FIG. 4 as follows. Every fourth pixel starting from 0, i.e. pixels, 0,4,8, . . . , 1148 of scan line 1 of the display screen frame occupy column locations 0,1, . . . , 287 of row 0 of the first memory array VRAM0 in BANK 1. Every fourth pixel starting from 1, i.e. pixels 1,5,9, . . . , 1149 of scan line 1 of the display screen frame occupy column locations 0,1, . . . , 287 of row 0 of the second memory array VRAM1 in BANK 1. Similarly, every fourth pixel starting from 2, i.e., pixels 2,6,10, . . . 1150 of scan line 1 of the display screen frame occupy column locations 0,1, . . . , 287 of row 0 of the third memory array VRAM2 of BANK 1. Finally, pixels 3,7,11, . . . , 1151 of scan line 1 of the display screen frame occupy column locations 0,1, . . . , 287 of row 0 of the fourth memory array VRAM3 of BANK 1.
In a similar manner, pixels 0,4,8, . . . , 1148 of scan line 2 of the display screen frame occupy column locations 0,1, . . . , 287 of row 1 of memory array VRAM0 of BANK 1. Pixels 1,5,9, . . . , 1149 of scan line 2 of the display screen frame occupy column locations 0,1, . . . , 287 of row 1 of memory array VRAM1 of BANK 1, and so on. Thus, the pixels of scan lines 1, . . . , 512 of the display screen frame occupy positions 0,1, . . . , 287 of rows 0,1, . . . , 511 of the memory arrays VRAM0, VRAM1, VRAM2, VRAM3 of BANK 1.
Scan lines 513,514, . . . , 900 of the display screen frame occupy positions 0,1, . . . , 287 of rows 0,1, . . . , 387 of the memory arrays VRAM0, VRAM1, VRAM2, VRAM3 of BANK 2 in a fashion similar to the storage in BANK 1. For instance, scan line 513 of the display screen frame is stored on row 0 of the memory arrays VRAM0, VRAM1, VRAM2, VRAM3 of BANK 2. Pixels 0,4,8, . . . , 1148 are stored in locations 0,1, . . . , 287 of row 0 of the first memory array VRAM0 of BANK 2. .Pixels 1,5,9, . . . , 1149 are stored in locations 0,1, . . . , 287 of row 0 of the second memory array VRAM1 of BANK 2, and so on. As can be seen from FIG. 4. 50.6% of the space in the VRAMs is unused.
Data is transmitted to the screen 12 of FIG. 3 from the memory of FIG. 4 as follows. To display scan line 1 of the display screen, during a vertical blanking interval, the row 0 of each memory array VRAM0, VRAM1, VRAM2, VRAM3 in BANK 1 is transferred to the SAM 46 (FIG. 2) in a read data transfer (RDT) operation. The data in the serial port, from locations 0,1, . . . , 287 is then transferred in bits-serial format to the screen. During the horizontal blanking interval following the display of the scan line 1 of the display screen, the pixel data in row 1 of each memory array VRAM 0, VRAM1, VRAM2, VRAM3 in BANK 1 is transferred to the SAM 46 (FIG. 2). The data stored at positions 0,1, . . . , 287 in the SAM 46 (FIG. 2) are then transferred serially to the screen to refresh scan line 2 of the screen display. Then scan lines 3,4, . . . , 512 of the screen display are refreshed in the same manner. The process continues until the scan line 513 of the display screen is refreshed. At this point, row 0 of each memory array VRAM0, VRAM1, VRAM2, VRAM3 in BANK 2 is transferred to the SAM 46 (FIG. 2) and the data of positions 0,1, . . . , 287 are serially transferred to the display screen. Then, scan lines 514, . . . , 900 of the display screen may be refreshed in a similar manner.
Alternatively, the pixel data may be stored in a special memory storage arrangement if a VRAM with split row transfer is used. A VRAM 60 with split transfer capability is illustrated in FIG. 5A. The VRAM 60 comprises a memory array, such as DRAM 62, which illustratively has 512 rows.times.512 columns. The columns are labeled near the top of FIG. 5A. The VRAM 60 includes a random access port 64 through which pixels may be written into the DRAM 62. The VRAM 60 also has a serial port 65 with split row transfer capability. Thus, the serial port 65 can perform both conventional read data transfer (RDT) operations and split row transfer operations. In a read data transfer, the SAM 66 acts as single shift register unit. A row of the DRAM 62 is addressed by loading a row address into the row address register 127. The gate units 67 and 68 are simultaneously enabled so that an entire addressed row of 512 pixels is transferred to the SAM 66. Pixels are transmitted serially via the serial I/O 73, starting at the position of column 0 in the SAM 66, synchronously with the serial counter 74. The outputted pixel data appear on line 75.
In a split row transfer operation, the SAM 66 is split into two halves 66A, 66B. The lower half 66A contains bit positions 0,1, . . . , 255 and the upper half 66b contains bit positions 256, 257, . . . , 511. In the case of a split row transfer only one of the gate units 67 or 68 is enabled so that only the upper half or the lower half of the VRAM 60 row addressed by the row address register 127 is transferred, respectively, to the upper half or the lower half of the SAM 66. A split row transfer operation makes use of the tap pointer implemented by the transfer control logic circuit 71. When a split read transfer cycle is initiated, the half of the SAM 66 pointed to by the tap pointer (i.e. upper or lower half) is loaded with the corresponding half row of data of the DRAM 62 currently addressed by the row address register 127. It should be noted that in a split row transfer operation, data may be transferred into one half of the SAM 66, while data is being read out of the other half. An example of a VRAM 60 with split row transfer capability is the TMS44C251 available from Texas Instruments.
As with the VRAM 40 (FIG. 3), the serial counter 74 has an input for receiving a starting location pointer for the serial output of the SAM 66. By means of this pointer, the SAM 66 will begin shifting out the pixel data from the location specified by this pointer. Thus, the serial output of the SAM 66 can be controlled to skip over selected pixel data.
Also depicted in FIG. 5A is a serial I/O control circuit 76. This circuit receives an input labeled SE which serves to enable or disable the I/O circuit 73. Thus, the serial output of the VRAM 60 may be selectively shut off.
FIG. 5B illustrates a special arrangement for storing the scan lines of pixel data of a 900*1152 display screen using 256K*4 VRAMs 60 (FIG. 6) which may execute a split row transfer. Here only one bank of 4 memory arrays, designated VRAM0, VRAM1, VRAM2, VRAM3, is used. As before, the display screen scan lines are labeled 1,2, . . . , 900, and the column locations within each scan line are labeled 0,1, . . . , 1151. The VRAM rows are labeled 0,1, . . . , 511 and the column locations of each row are labeled 0,1, . . . , 511.
The rows of each memory array VRAM0,VRAM1,VRAM2,VRAM3 are divided in half. The lower half of each array row, i.e., locations 0,1, . . . , 255, is used for storing the first 1024 pixel data of the odd scan lines of the display screen. The upper half, i.e. locations 256,257, . . . , 511 is used for storing the first 1024 pixel data of the even scan lines of the display screen.
The storage of the pixels is as follows. The first 1024 pixels, i.e. 0,1, . . . , 1023, of scan line 1 of the display screen are stored in column positions 0,1, . . . , 255 of row 0 of the memory arrays VRAM0, VRAM1, VRAM2, VRAM3. As before, every fourth pixel from 0, i.e. 0,4, 8, . . . , 1020 is stored in locations 0,1, . . . , 255 of row 0 of the first memory array VRAM0. Likewise, every fourth pixel from 1, i.e. 1,5,9, . . . , 1021 of the display screen is stored in locations 0,1, . . . , 255 of row 0 of the second array VRAM1. Every fourth pixel from 2, i.e. 2,6,10, . . . , 1022 is stored in locations 0,1, . . . , 255 of the third array VRAM2. Finally, every fourth pixel from 3, i.e. 3,7,11, . . . , 1023 is stored in locations 0,1, . . . , 255 of the fourth array VRAM3.
The first 1024 pixels of the remaining odd scan lines 3,5, . . . , 899 of the display screen are stored in column positions 0,1, . . . , 255 of the four memory arrays VRAM0, VRAM1, VRAM2, VRAM3 in a similar fashion. In other words, the first 1024 pixels of the odd scan lines occupy the lower half of the rows 0,1, . . . , 449 of the four memory arrays VRAM0, VRAM1, VRAM2, VRAM3.
The last one hundred twenty-eight pixels of each odd display screen scan line, i.e. pixels 1024,1025, . . . , 1151, are stored in the upper half of the bottom rows, i.e. 511,510, . . . , 454 of the memory arrays VRAM0, VRAM1, VRAM2, VRAM3. Pixels 1024,1028, . . . , 1048 of scan line 1 of the display screen are stored in column locations 256,257, . . . , 289 of row 511 of the first memory array VRAM0. Pixels 1025,1029, . . . , 1049 of scan line 1 of the display screen are stored in column locations 256,257, . . . , 289 of row 511 of the second memory array VRAM1. Pixels 1026,1030, . . . , 1050 of scan line 1 of the display screen are stored in column locations 256,257, . . . , 289 of row 511 of the third memory array VRAM2. Finally, pixels 1027,1031, . . . , 1051 of scan line 1 of the display screen are stored in column locations 256,257, . . . , 289 of row 511 of the fourth memory array VRAM3.
In a similar fashion, the last one hundred twenty-eight pixels of the third display screen scan line are stored in the thirty-two column locations adjacent the last 128 pixels of the first scan line, i.e. locations 290,291, . . . , 321. Thus, the last one hundred twenty-eight pixels of scan lines 1,3,5,7,9,11,13,15 of the display screen are stored in the upper half of row 511 of the memory arrays VRAM0, VRAM1, VRAM2, VRAM3. Scan lines 17,19,21,23,25,27,29,31 of the display screen are stored in the upper half of row 510 of the memory arrays VRAM0, VRAM1, VRAM2, VRAM3. In this fashion, the last one hundred twenty-eight pixels of each odd display screen scan line are stored in the upper half of the memory arrays VRAM0, VRAM1, VRAM2, VRAM3 from row 511 to row 454.
The storage of the even scan lines of pixels of the display screen is as follows. Pixels 0,1, . . . , 1023 of scan line 2 of the display screen are stored in column positions 256,257, . . . , 511 of row 0 of the four memory arrays VRAM0, VRAM1, VRAM2, VRAM 3 in a fashion similar to row 1 of the display screen. That is, pixels 0,4,8, . . . , 1020 of scan line 2 of the screen display are stored in row 0, positions 256,257, . . . , 511 of the first memory array VRAM0. Pixels 1,5,9, . . . , 1021 of scan line 2 of the screen display are stored in row 0, positions 256,257, . . . , 511 of the second memory array VRAM1. Pixels 2,6,10, . . . , 1022 of scan line 2 of the display screen are stored in row 0, positions 256,257, . . . , 511 of the third memory array VRAM2. Finally, pixels 3,7,11, . . . , 1023 of scan line 2 of the display screen are stored in row 0, positions 256,257, . . . , 511 of the fourth memory array VRAM3.
The first 1024 pixels of each even scan line 2,4,6, . . . , 900 of the display screen are stored in column positions 256,257, . . . , 511 of the four memory arrays VRAM0, VRAM1, VRAM2, VRAM3 in a similar fashion. In other words, the first 1024 pixels of the even scan lines occupy the upper half of the rows 0,1, . . . , 449 of the four memory arrays VRAM0, VRAM1, VRAM2, VRAM3.
The last one hundred twenty-eight pixels of each even display screen scan line, i.e. pixels 1024,1025, . . . , 1151 are stored in the lower half of the bottom rows 511,510, . . . , 454 of the memory arrays VRAM0, VRAM1, VRAM2, VRAM3. Pixels 1024,1028, . . . , 1148 of scan line 2 of the display screen are stored in column locations 0,1, . . . , 31 of row 511 of the first memory array VRAM0. Pixels 1025,1029, . . . , 1149 of scan line 2 of the display screen are stored in column locations 0,1, . . . , 31 of row 511 of the second memory array VRAM1. Pixels 1026,1030, . . . , 1150 of scan line 2 of the display screen are stored in column locations 0,1, . . . , 31 of row 511 of the third memory array VRAM2. Finally, pixels 1027,1031, . . . , 1151 of scan line 2 of the display screen are stored in column locations 0,1, . . . , 31 of row 511 of the fourth memory array VRAM3.
In a similar fashion, the last one hundred pixels of the fourth scan line of the display screen are stored in the thirty-two column locations adjacent the last one hundred twenty-eight pixels of the scan line 2, i.e. locations 32,33, . . . , 63. Thus, the last one hundred twenty-eight pixels of scan lines 2,4,6,8,10,12,14,16 of the display screen are stored in the lower half of row 511 of the memory arrays VRAM0, VRAM1, VRAM2, VRAM3. Scan lines 18,20,22,24,26,28,30,32 of the display screen are stored in the lower half of row 510 of the memory arrays VRAM0, VRAM1, VRAM2, VRAM3. In this fashion, the last one hundred twenty-eight pixels of each even display screen scan line are stored in the lower half of the memory arrays VRAM0, VRAM1, VRAM2, VRAM3 from row 511 to row 454.
The screen refresh operation is slightly different than with the example of FIG. 4 before. To display scan line 1 of the display screen, a split row transfer is executed to move the lower half of row 0 of the DRAM 62 (FIG. 5A) into the SAM 66 (FIG. 5A). Thus, after this transfer, the SAM 66 (FIG. 5A) stores the first 1024 pixels of scan line 1 in its lower half. While the data of this half row is serially outputted from the VRAM 60 (FIG. 5A), another split row transfer is performed to move the data of the upper half of row 511 of the DRAM 62 (FIG. 5A) into the SAM 66 (FIG. 5A), including the last one hundred twenty-eight pixels of scan line 1. Thus, after the lower half row is outputted from the SAM 66 (FIG. 5A), the serial counter pointer may be set to point to the location in the SAM 66 of the first of the last one hundred twenty-eight pixels. The last one hundred pixels of scan line 1 of the display screen may thereafter be serially outputted from the VRAM 60 (FIG. 5A).
After the display of display screen scan line 1, a horizontal blanking interval occurs. The upper half of row 0 of the DRAM 62 (FIG. 5A) (containing the first 1024 pixels of display screen scan line 2) is transferred, Via a split row transfer to the upper half of the SAM 66 (FIG. 5A). The serial counter pointer is set to point to the first pixel datum of the upper half and pixels are shifted out of the SAM (FIG. 5A). While pixel data are serially shifted out of the upper half of the SAM 66 (FIG. 5A) a split row transfer is performed to move the last one hundred twenty-eight pixels of display screen scan line 2 from the lower half of DRAM 62 (FIG. 5A) row 511 to the lower half of the SAM 66 (FIG. 5A). Again, after pixel 1024 of the display screen row is shifted out, the serial counter pointer may be set to point to the location of the first of the one hundred twenty-eight pixels in the lower half of the SAM 66 (FIG. 5A). The last one hundred twenty-eight pixels of scan line 2 may then be shifted out. This process continues for all of the display screen scan lines.
As can be seen, the circuit of FIG. 5B uses much of the VRAM 60 (FIG. 5) without wasting space. However, the display of pixels on the display screen is highly complex. The complexity increases for displays of dimensions not divisible by 32, or displays having odd dimensions.
In view of the foregoing, it is an object of the present invention to provide a display system which makes more efficient use of memory resources.
It is also an object of the invention to provide a video display system whose structure is independent of a specific screen resolution.
It is a further object of the invention to provide a video display system which is adaptable to any screen resolution without complicated circuitry.